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12-Bit CCD Signal Processor with Precision Timing Core AD9949
FEATURES
New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA(R)) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision TimingTM core with < 600 ps resolution On-chip 3 V horizontal and RG drivers 40-lead LFCSP package
GENERAL DESCRIPTION
The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of -20C to +85C.
APPLICATIONS
Digital still cameras High speed digital imaging applications
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
0dB TO 18dB CCDIN CDS PxGA
6dB TO 42dB VGA
VREF 12-BIT ADC 12 DOUT
CLAMP INTERNAL CLOCKS
HBLK CLP/PBLK
RG H1 TO H4 4 HORIZONTAL DRIVERS
PRECISION TIMING CORE
CLI
AD9949
SYNC GENERATOR
INTERNAL REGISTERS
03751-001
HD
VD
SL
SCK SDATA
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9949 TABLE OF CONTENTS
Specifications..................................................................................... 3 General Specifications ................................................................. 3 Digital Specifications ................................................................... 3 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Equivalent Input/Output Circuits .................................................. 9 Typical Performance Characteristics ........................................... 10 System Overview ............................................................................ 11 H-Counter Behavior .................................................................. 11 Serial Interface Timing .................................................................. 12 Complete Register Listing ............................................................. 13 Precision Timing High Speed Timing Generation...................... 18 Timing Resolution...................................................................... 18 High Speed Clock Programmability ........................................ 18 H-Driver and RG Outputs ........................................................ 19 Digital Data Outputs.................................................................. 19 Horizontal Clamping and Blanking ............................................. 21 Individual CLPOB and PBLK Sequences................................ 21 Individual HBLK Sequences..................................................... 21 Generating Special HBLK Patterns .............................................. 23 Horizontal Sequence Control ................................................... 23 External HBLK Signal................................................................ 23 H-Counter Synchronization ..................................................... 24 Power-Up Procedure...................................................................... 25 Recommended Power-Up Sequence ....................................... 25 Analog Front End Description and Operation .......................... 26 DC Restore .................................................................................. 26 Correlated Double Sampler ...................................................... 26 PxGA............................................................................................ 26 Variable Gain Amplifier ............................................................ 29 ADC ............................................................................................. 29 Optical Black Clamp .................................................................. 29 Digital Data Outputs.................................................................. 29 Applications Information .............................................................. 30 Circuit Configuration ................................................................ 30 Grounding and Decoupling Recommendations.................... 30 Driving the CLI Input................................................................ 31 Horizontal Timing Sequence Example.................................... 31 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34
REVISION HISTORY
11/04--Data Sheet Changed from Rev. A to Rev. B Changes to Ordering Guide .......................................................... 35 9/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Analog Specifications .................................................. 4 Changes to Terminology Section.................................................... 9 Added H-Counter Behavior Section............................................ 12 Changes to Table 7.......................................................................... 14 Changes to Table 12 ....................................................................... 17 Changes to Table 15 ....................................................................... 17 Changes to H-Counter Sync Section ........................................... 24 Changes to Recommended Power-Up Sequence Section ......... 25 Changes to Ordering Guide .......................................................... 35 5/03--Revision 0: Initial Version
Rev. B | Page 2 of 36
AD9949 SPECIFICATIONS
GENERAL SPECIFICATIONS
Table 1.
Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1 to H4 Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DVDD (All Other Digital) POWER DISSIPATION 36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 Total Shutdown Mode Min -20 -65 36 2.7 2.7 2.7 2.7 2.7 3.0 3.0 3.0 3.0 3.0 320 1 Typ Max +85 +150 Unit C C MHz V V V V V mW mW
3.6 3.6 3.6 3.6 3.6
1
The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H - Outputs Used) Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation.
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted. Table 2.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) Low Level Input Voltage RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD - 0.5 V and HVDD - 0.5 V) Low Level Output Voltage Maximum Output Current (Programmable) Maximum Load Capacitance Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 Typ Max Unit V V A A pF V V
VIH-CLI VIL-CLI
1.85 0.85
V V
VOH VOL
2.2 0.5 30 100
V V mA pF
Rev. B | Page 3 of 36
AD9949
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless otherwise noted. Table 3.
Parameter CDS Gain Allowable CCD Reset Transient1 Maximum Input Range before Saturation1 Maximum CCD Black Pixel Amplitude1 PIXEL GAIN AMPLIFIER (PxGA) Gain Control Resolution Gain Monotonicity Minimum Gain Maximum Gain VARIABLE GAIN AMPLIFIER (VGA) Maximum Input Range Maximum Output Range Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code 0) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (0) Maximum Clamp Level (255) A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Integral Nonlinearity (INL) Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE VGA Gain Accuracy Minimum Gain (Code 0) Maximum Gain (Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 0 500 1.0 50 256 0 18 1.0 2.0 1024 Guaranteed 6 42 256 0 255 12 -1.0 Max Unit dB mV V p-p mV Steps dB dB V p-p V p-p Steps Notes
dB dB Steps Measured at ADC output LSB LSB Bits LSB LSB V V V Specifications include entire signal chain
0.5 Guaranteed 2.0 2.0 1.0
+1.0 8
5.0 40.5
5.5 41.5 0.15 0.8 50
6.0 42.5 0.6
dB dB % LSB rms dB
12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply
1
Input signal characteristics defined as follows:
50mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
03751-002
500mV TYP RESET TRANSIENT
Rev. B | Page 4 of 36
AD9949
TIMING SPECIFICATIONS
CL = 20 pF, fCLI = 36 MHz, unless otherwise noted. Table 4.
Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period CLI High/Low Pulse Width Delay from CLI to Internal Pixel Period Position CLPOB PULSE WIDTH (PROGRAMMABLE)1 SAMPLE CLOCKS (See Figure 18) SHP Rising Edge to SHD Rising Edge DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay From Programmed Edge Pipeline Delay SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Symbol tCLI tADC tCLIDLY tCOB tS1 tOD Min 27.8 11.2 2 12.5 Typ Max Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns
13.9 6 20 13.9 6 11
16.6
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Rev. B | Page 5 of 36
AD9949 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD and TCVDD HVDD and RGVDD DVDD and DRVDD Any VSS Digital Outputs CLPOB/PBLK and HBLK SCK, SL, and SDATA RG H1 to H4 REFT, REFB, and CCDIN Junction Temperature Lead Temperature (10 s) With Respect to AVSS HVSS, RGVSS DVSS, DRVSS Any VSS DRVSS DVSS DVSS RGVSS HVSS AVSS Rating -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to RGVDD + 0.3 V -0.3 V to HVDD + 0.3 V -0.3 V to AVDD + 0.3 V 150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance 40-Lead LFCSP Package: JA = 27C/W1.
1
JA is measured using a 4-layer PCB with the exposed paddle soldered to the board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 36
AD9949 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 D0 (LSB) 39 CLP/PBLK 38 HBLK 37 DVDD 36 DVSS 35 HD 34 VD 33 SCK 32 SDI 31 SL
D1 1 D2 2 D3 3 D4 4 DRVSS 5 DRVDD 6 D5 7 D6 8 D7 9 D8 10
PIN 1 INDICATOR
AD9949
TOP VIEW
30 REFB 29 REFT 28 AVSS 27 CCDIN 26 AVDD 25 CLI 24 TCVDD 23 TCVSS 22 RGVDD 21 RG
D9 11 D10 12 (MSB) D11 13 H1 14 H2 15 HVSS 16 HVDD 17 H3 18 H4 19 RGVSS 20
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 to 4 5 6 7 to 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Mnemonic D1 to D4 DRVSS DRVDD D5 to D11 H1 H2 HVSS HVDD H3 H4 RGVSS RG RGVDD TCVSS TCVDD CLI AVDD CCDIN AVSS REFT REFB SL SDI SCK VD HD DVSS DVDD HBLK CLP/PBLK D0 Type1 DO P P DO DO DO P P DO DO P DO P P P DI P AI P AO AO DI DI DI DI DI P P DI DO DO Description Data Outputs Digital Driver Ground Digital Driver Supply Data Outputs (D11 is MSB) CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1 to H4 Driver Ground H1 to H4 Driver Supply CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Ground for Timing Core Analog Supply for Timing Core Master Clock Input Analog Supply for AFE Analog Input for CCD Signal (Connect through Series 0.1 F Capacitor) Analog Ground for AFE Reference Top Decoupling (Decouple with 1.0 F to AVSS) Reference Bottom Decoupling (Decouple with 1.0 F to AVSS) 3-Wire Serial Load 3-Wire Serial Data Input 3-Wire Serial Clock Vertical Sync Pulse Horizontal Sync Pulse Digital Ground Digital Supply Optional HBLK Input CLPOB or PBLK Output Data Output LSB
1
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
Rev. B | Page 7 of 36
03751-003
AD9949 TERMINOLOGY
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Integral Nonlinearity (INL) INL is the deviation of each individual code measured from a true straight line from zero to full scale. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9949 from a straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the straight line reference. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is appropriately gained up to fill the ADC's full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC full scale/2n codes) where n is the bit resolution of the ADC. For the AD9949, 1 LSB is approximately 0.488 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
Rev. B | Page 8 of 36
AD9949 EQUIVALENT INPUT/OUTPUT CIRCUITS
AVDD
DVDD
R
330
03751-004
AVSS
AVSS
DVSS
Figure 3. CCDIN (Pin 27)
AVDD
Figure 6. Digital Inputs (Pins 31 to 35, 38)
HVDD OR RGVDD
CLI
330
25k + 1.4V
03751-005
DATA
AVSS
ENABLE
03751-007
DOUT
Figure 4. CLI (Pin 25)
03751-008
DVSS
DRVDD
HVSS OR RGVSS
DATA
Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21)
THREE-STATE
DOUT
DVSS
DRVSS
Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40)
Rev. B | Page 9 of 36
03751-006
AD9949 TYPICAL PERFORMANCE CHARACTERISTICS
1.0
400
POWER DISSIPATION (mW)
0.5
350
DNL (LSB)
300 VDD = 3.3V VDD = 3.0V 250 VDD = 2.7V 200
0
-0.5
03751-009
0
500
1000
1500 2000 2500 3000 ADC OUTPUT CODE
3500
4000
24 30 SAMPLE RATE (MHz)
36
Figure 8. Typical DNL
48
Figure 10. Power Curves
40
OUTPUT NOISE (LSB)
32
24
16
8
0
200
400 600 VGA GAIN CODE (LSB)
800
1000
Figure 9. Output Noise vs. VGA Gain
03751-010
0
Rev. B | Page 10 of 36
03751-011
-1.0
150 18
AD9949 SYSTEM OVERVIEW
V-DRIVER V1 TO Vx, VSG1 TO VSGx, SUBCK H1 TO H4, RG DOUT CCDIN DIGITAL IMAGE PROCESSING ASIC
H-COUNTER BEHAVIOR
When the maximum horizontal count of 4096 pixels is exceeded, the H-counter in the AD9949 rolls over to zero and continues counting. It is, therefore, recommended that the maximum counter value not be exceeded. However, the newer AD9949A version behaves differently. In the AD9949A, the internal H-counter holds at its maximum count of 4095 instead of rolling over. This feature allows the AD9949A to be used in applications containing a line length greater than 4096 pixels. Although no programmable values for the horizontal blanking or clamping are available beyond pixel 4095, the H, RG, and AFE clocking continues to operate, sampling the remaining pixels on the line.
MAXIMUM FIELD DIMENSIONS
CCD
AD9949
INTEGRATED AFE + TD HD, VD
CLI SERIAL INTERFACE
03751-012
Figure 11. Typical Application
The H-drivers for H1 to H4 and RG are included in the AD9949, allowing these clocks to be directly connected to the CCD. The H-drive voltage of 3 V is supported in the AD9949. Figure 12 shows the horizontal and vertical counter dimensions for the AD9949. All internal horizontal clocking is programmed using these dimensions to specify line and pixel locations.
Figure 12. Vertical and Horizontal Counters
MAX VD LENGTH IS 4095 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
Figure 13. Maximum VD/HD Dimensions
Rev. B | Page 11 of 36
03751-014
CLI
03751-013
Figure 11 shows the typical system application diagram for the AD9949. The CCD output is processed by the AD9949's AFE circuitry, which consists of a CDS, a PxGA, a VGA, a black level clamp, and an ADC. The digitized pixel information is sent to the digital image processor chip where all postprocessing and compression occurs. To operate the CCD, CCD timing parameters are programmed into the AD9949 from the image processor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor, the AD9949 generates the high speed CCD clocks and all internal AFE clocks. All AD9949 clocks are synchronized with VD and HD. The AD9949's horizontal pulses (CLPOB, PBLK, and HBLK) are programmed and generated internally.
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
AD9949 SERIAL INTERFACE TIMING
The AD9949's internal registers are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data-word are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 14. Although many registers are less than 24 bits wide, all 24 bits must be written for each register. If the register is only 16 bits wide, then the upper eight bits may be filled with zeros during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data. Figure 15 shows a more efficient way to write to the registers by using the AD9949's address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit data-word is written automatically to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Address auto-increment may be used starting with any register location and may be used to write to as few as two registers or as many as the entire register space.
8-BIT ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3
24-BIT DATA
... ...
D21 D22
D23
tDS
SCK 1 2 3 4 5 6
tDH
7 8 9 10 11 12 30 31 32
tLS
SL
tLH
... ...
SL UPDATED VD/HD UPDATED
VD
...
HD NOTES 1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON'T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH. 4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. 5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 14. Serial Write Operation
DATA FOR STARTING REGISTER ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1
DATA FOR NEXT REGISTER ADDRESS D23 D0 D1
... ... ...
D22
... ... ...
D22
D23
D0
D1
D2
... ... ...
03751-016
SCK
1
2
3
4
5
6
7
8
9
10
31
32
33
34
55
56
57
58
59
SL
NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 15. Continuous Serial Write Operation
Rev. B | Page 12 of 36
03751-015
AD9949 COMPLETE REGISTER LISTING
1. 2. All addresses and default values are expressed in hexadecimal. All registers are VD/HD updated as shown in Figure 14, except for the registers indicated in Table 7, which are SL updated. Table 7. SL Updated Registers
Register OPRMODE CTLMODE SW_RESET TGCORE _RSTB PREVENTUPDATE VDHDEDGE FIELDVAL HBLKRETIME CLPBLKOUT CLPBLKEN H1CONTROL RGCONTROL DRVCONTROL SAMPCONTROL DOUTPHASE Description AFE Operation Modes AFE Control Modes Software Reset Bit Reset Bar Signal for Internal TG Core Prevents Update of Registers VD/HD Active Edge Resets Internal Field Pulse Retimes the HBLK to Internal Clock CLP/BLK Output Pin Select Enables CLP/BLK Output Pin H1/H2 Polarity/Edge Control RG Polarity/Edge Control RG and H1 to H4 Drive Current SHP/SHD Sampling Edge Control Data Output Phase Adjustment
Rev. B | Page 13 of 36
AD9949
Table 8. AFE Register Map
Address 00 01 02 03 04 05 Data Bit Content [11:0] [9:0] [7:0] [11:0] [17:0] [17:0] Default Value 4 0 80 4 0 0 Name OPRMODE VGAGAIN CLAMP LEVEL CTLMODE PxGA GAIN01 PxGA GAIN23 Description AFE Operation Modes. (See Table 14.) VGA Gain. Optical Black Clamp Level. AFE Control Modes. (See Table 15.) PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9]. PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].
Table 9. Miscellaneous Register Map
Address 10 11 12 Data Bit Content [0] [0] [0] Default Value 0 0 0 Name SW_RST OUT_CONTROL TGCORE_RSTB Description Software Reset. 1 = Reset all registers to default, then self-clear back to 0. Output Control. 0 = Make all dc outputs inactive. Timing Core Reset Bar. 0 = Reset TG core. 1 = Resume operation. Serial Update. Sets the line (HD) within the field to update serial data. Prevents the update of the VD updated registers. 1 = Prevent Update. VD/HD Active Edge. 0 = Falling Edge Triggered. 1 = Rising Edge Triggered. Field Value Sync. 0 = Next Field 0. 1 = Next Field 1. 2/3 = Next Field 2. Retime HBLK to Internal H1 Clock. Preferred setting is 1. Setting to 1 adds one cycle delay to HBLK toggle positions. CLP/BLK Pin Output Select. 0 = CLPOB. 1 = PBLK. 2 = HBLK. 3 = Low. Enable CLP/BLK Output. 1 = Enable. Internal Test Mode. Should always be set high.
13 14 15
[11:0] [0] [0]
0 0 0
UPDATE PREVENTUPDATE VDHDEDGE
16
[1:0]
0
FIELDVAL
17
[0]
0
HBLKRETIME
18
[1:0]
0
CLPBLKOUT
19 1A
[0] [0]
1 0
CLPBLKEN TEST MODE
Rev. B | Page 14 of 36
AD9949
Table 10. CLPOB Register Map
Address 20 21 22 23 24 25 26 27 28 Data Bit Content [3:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0] Default Value (Hex) F FFFFFF FFFFFF FFFFFF FFFFFF 0 0 FFF FFF FFF Name CLPOBPOL CLPOBTOG_0 CLPOBTOG_1 CLPOBTOG_2 CLPOBTOG_3 CLPOBSCP0 CLPOBSPTR CLPOBSCP1 CLPOBSCP2 CLPOBSCP3 Description Start Polarities for CLPOB Sequences 0, 1, 2, and 3. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. CLPOB Sequence-Change Position 0 (Hard-Coded to 0). CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2[5:4], 3[7:6]. CLPOB Sequence-Change Position 1. CLPOB Sequence-Change Position 2. CLPOB Sequence-Change Position 3.
Table 11. PBLK Register Map
Address 30 31 32 33 34 35 36 37 38 Data Bit Content [3:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0] Default Value (Hex) F FFFFFF FFFFFF FFFFFF FFFFFF 0 0 FFF FFF FFF Name PBLKPOL PBLKTOG_0 PBLKTOG_1 PBLKTOG_2 PBLKTOG_3 PBLKSCP0 PBLKSPTR PBLKSCP1 PBLKSCP2 PBLKSCP3 Description Start Polarities for PBLK Sequences 0, 1, 2, and 3. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. PBLK Sequence-Change Position 0 (Hard-Coded to 0). PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. PBLK Sequence-Change Position 1. PBLK Sequence-Change Position 2. PBLK Sequence-Change Position 3.
Rev. B | Page 15 of 36
AD9949
Table 12. HBLK Register Map
Address 40 Data Bit Content [0] Default Value (Hex) 0 Name HBLKDIR Description HBLK Internal/External. 0 = Internal. 1 = External. HBLK External Active Polarity. 0 = Active Low. 1 = Active High. HBLK External Masking Polarity. 0 = Mask H1 Low. 1 = Mask H1High. HBLK Internal Masking Polarity for Each Sequence 0 to 3. 0 = Mask H1 Low. 1 = Mask H1 High. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6[23:12]. HBLK Sequence-Change Position 0 (Hard-coded to 0). HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. HBLK Sequence-Change Position 1. HBLK Sequence-Change Position 2. HBLK Sequence-Change Position 3.
41
[0]
0
HBLKPOL
42
[0]
1
HBLKEXTMASK
43
[3:0]
F
HBLKMASK
44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
[23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0]
FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF 0 0 FFF FFF FFF
HBLKTOG12_0 HBLKTOG34_0 HBLKTOG56_0 HBLKTOG12_1 HBLKTOG34_1 HBLKTOG56_1 HBLKTOG12_2 HBLKTOG34_2 HBLKTOG56_2 HBLKTOG12_3 HBLKTOG34_3 HBLKTOG56_3 HBLKSCP0 HBLKSPTR HBLKSCP1 HBLKSCP2 HBLKSCP3
Table 13. H1 to H2, RG, SHP, SHD Register Map
Address 60 Data Bit Content [12:0] Default Value 01001 Name H1CONTROL Description H1 Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion). H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7]. RG Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion). RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7]. Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA. SHP/SHD Sample Control. SHP Sampling Location [5:0]. SHD Sampling Location [11:6]. DOUT Phase Control.
61
[12:0]
00801
RGCONTROL
62
[14:0]
0
DRVCONTROL
63 64
[11:0] [5:0]
00024 0
SAMPCONTROL DOUTPHASE
Rev. B | Page 16 of 36
AD9949
Table 14. AFE Operation Register Detail
Address 00 Data Bit Content [1:0] Default Value 0 Name PWRDOWN Description 0 = Normal Operation. 1 = Reference Standby. 2/3 = Total Power-Down 0 = Disable OB Clamp. 1 = Enable OB Clamp. 0 = Select Normal OB Clamp Settling. 1 = Select Fast OB Clamp Settling. 0 = Ignore VGA Update. 1 = Very Fast Clamping when VGA Is Updated. DOUT Value during PBLK. 0 = Blank to Zero. 1 = Blank to Clamp Level. Test Operation Only. Set to zero. 0 = Enable DC restore circuit. 1 = Bypass DC Restore Circuit during PBLK. Test Operation Only. Set to zero. Adjustment of CDS Gain. 0 = 0 dB. 01 = -2 dB. 10 = -4 dB. 11 = 0 dB.
[2] [3] [4] [5]
1 0 0 0
CLPENABLE CLPSPEED FASTUPDATE PBLK_LVL
[7:6] [8] [9] [11:10]
0 0 0 0
TEST MODE DCBYP TESTMODE CDSGAIN
Table 15. AFE Control Register Detail
Address 03 Data Bit Content [1:0] Default Value 0 Name COLORSTEER Description 0 = Off. 1 = Progressive. 2 = Interlaced. 3 = Three Field. 0 = Disable PxGA. 1 = Enable PxGA. 0 = Data Outputs Are Driven. 1 = Data Outputs Are Three-Stated. 0 = Latch Data Outputs with DOUT Phase. 1 = Output Latch Transparent. 0 = Binary Encode Data Outputs. 1 = Gray Encode Data Outputs.
[2] [3] [4] [5]
1 0 0 0
PxGAENABLE DOUTDISABLE DOUTLATCH GRAYENCODE
Rev. B | Page 17 of 36
AD9949 PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9949 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG, H1 to H4, SHP, and SHD, are generated. The RG pulse has programmable rising and falling edges and may be inverted using the polarity control. The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table 16 summarizes the high speed timing registers and their parameters. Each edge location setting is 6 bits wide, but only 48 valid edge locations are available. Therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. Table 17 shows the correct register values for the corresponding edge locations.
TIMING RESOLUTION
The Precision Timing core uses a 1x master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 16 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Therefore, the edge resolution of the Precision Timing core is (tCLI/48). For more information on using the CLI input, refer to the Applications Information section.
POSITION CLI
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
tCLIDLY
1 PIXEL PERIOD
...
...
NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. t 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS ( CLIDLY = 6 ns TYP).
Figure 16. High Speed Clock Resolution from CLI Master Clock Input
3 CCD SIGNAL 4
1 RG 5 H1/H3
2
6
H2/H4 PROGRAMMABLE CLOCK POSITIONS: 1. RG RISING EDGE. 2. RG FALLING EDGE. 3. SHP SAMPLE LOCATION. 4. SHD SAMPLE LOCATION. 5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).
Figure 17. High Speed Clock Programmable Locations
Rev. B | Page 18 of 36
03751-018
03751-017
AD9949
Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter Polarity Positive Edge Negative Edge Sample Location Drive Control DOUT Phase Length 1b 6b 6b 6b 3b 6b Range High/Low 0 to 47 Edge Location 0 to 47 Edge Location 0 to 47 Sample Location 0 to 7 Current Steps 0 to 47 Edge Location Description Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion). Positive Edge Location for H1/H3 and RG. Negative Edge Location for H1/H3 and RG. Sampling Location for SHP and SHD. Drive Current for H1 to H4 and RG Outputs, 0 to 7 Steps of 4.1 mA Each. Phase Location of Data Outputs with Respect to Pixel Period.
Table 17. Precision Timing Edge Locations
Quadrant I II III IV Edge Location (Decimal) 0 to 11 12 to 23 24 to 35 36 to 47 Register Value (Decimal) 0 to 11 16 to 27 32 to 43 48 to 59 Register Value (Binary) 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
H-DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9949 features on-chip output drivers for the RG and H1 to H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG driver current can be adjusted for optimum rise/fall time into a particular load by using the DRVCONTROL register (Address 0x62). The DRVCONTROL register is divided into five different 3-bit values, each one being adjustable in 4.1 mA increments. The minimum setting of 0 is equal to OFF or three-state, and the maximum setting of 7 is equal to 30.1 mA. As shown in Figure 18, the H2/H4 outputs are inverses of H1/H3. The internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1/H2 crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable.
DIGITAL DATA OUTPUTS
The AD9949 data output phase is programmable using the DOUTPHASE register (Address 0x64). Any edge from 0 to 47 may be programmed, as shown in Figure 19. The pipeline delay for the digital data output is shown in Figure 20.
H1/H3
tRISE
H2/H4
tPD << tRISE
H1/H3 FIXED CROSSOVER VOLTAGE
tPD
H2/H4
03751-019
Figure 18. H-Clock Inverse Phase Relationship
Rev. B | Page 19 of 36
AD9949
P[0] CLI 1 PIXEL PERIOD P[12] P[24] P[36] P[48] = P[0]
tOD
DOUT
NOTES 1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
Figure 19. Digital Output Phase Adjustment
CLI
tCLIDLY
N-1 CCDIN SAMPLE PIXEL N SHD (INTERNAL) PIPELINE LATENCY = 11 CYCLES DOUT N - 13 N - 12 N - 11 N - 10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N N+1
03751-021
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
NOTES 1. DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0. 2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 20. Pipeline Delay for Digital Data Output
Rev. B | Page 20 of 36
03751-020
AD9949 HORIZONTAL CLAMPING AND BLANKING
The AD9949's horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. signals are active low and should be programmed accordingly. Up to four individual sequences can be created for each signal.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing shown in Figure 22 is similar to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and the stop positions of the blanking period. Additionally, there is a polarity control, HBLKMASK, which designates the polarity of the horizontal clock signals H1 to H4 during the blanking period. Setting HBLKMASK high sets H1 = H3 = low and H2 = H4 = high during the blanking, as shown in Figure 23. Up to four individual sequences are available for HBLK.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 21. These two signals are independently programmed using the parameters shown in Table 18. The start polarity, first toggle position, and second toggle position are fully programmable for each signal. The CLPOB and PBLK
HD
...
2 CLPOB 1 PBLK ACTIVE 3 ACTIVE
...
03751-022
PROGRAMMABLE SETTINGS: 1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW). 2. FIRST TOGGLE POSITION. 3. SECOND TOGGLE POSITION.
Figure 21. Clamp and Preblank Pulse Placement
...
HD 1 HBLK BLANK 2 BLANK
...
03751-023
PROGRAMMABLE SETTINGS: 1. FIRST TOGGLE POSITION = START OF BLANKING. 2. SECOND TOGGLE POSITION = END OF BLANKING.
Figure 22. Horizontal Blanking (HBLK) Pulse Placement
Table 18. CLPOB and PBLK Individual Sequence Parameters
Parameter Polarity Toggle Position 1 Toggle Position 2 Length 1b 12b 12b Range High/Low 0 to 4095 Pixel Location 0 to 4095 Pixel Location Description Starting Polarity of Clamp and PBLK Pulses for Sequences 0 to 3. First Toggle Position within the Line for Sequences 0 to 3. Second Toggle Position within the Line for Sequences 0 to 3.
Table 19. HBLK Individual Sequence Parameters
Parameter HBLKMASK Toggle Position 1 Toggle Position 2 Toggle Position 3 Toggle Position 4 Toggle Position 5 Toggle Position 6 Length 1b 12b 12b 12b 12b 12b 12b Range High/Low 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location 0 to 4095 Pixel Location Description Masking Polarity for H1 for Sequences 0 to 3 (0 = H1 Low, 1 = H1 High). First Toggle Position within the Line for Sequences 0 to 3. Second Toggle Position within the Line for Sequences 0 to 3. Third Toggle Position within the Line for Sequences 0 to 3. Fourth Toggle Position within the Line for Sequences 0 to 3. Fifth Toggle Position within the Line for Sequences 0 to 3. Sixth Toggle Position within the Line for Sequences 0 to 3.
Rev. B | Page 21 of 36
AD9949
...
HD
...
HBL K
H1/H3
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
...
H1/H3
03751-024
H2/H4
...
Figure 23. HBLK Masking Control
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
HBLK
H1/H3
H2/H4
03751-025
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure 24. Generating Special HBLK Patterns
Table 20. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK
Register SCP SPTR Length 12b 2b Range 0 to 4095 Line Number 0 to 3 Sequence Number Description CLOB/PBLK/HBLK SCP to Define Horizontal Regions 0 to 3. Sequence Pointer for Horizontal Regions 0 to 3.
Rev. B | Page 22 of 36
AD9949 GENERATING SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as shown in Figure 24. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created. CLPOB, PBLK, and HBLK each have a separate set of SCPs. For example, CLPOBSCP1 defines Region 0 for CLPOB, and in that region any of the four individual CLPOB sequences may be selected with the CLPOBSPTR register. The next SCP defines a new region and in that region, each signal can be assigned to a different individual sequence. The sequence control registers are summarized in Table 20.
HORIZONTAL SEQUENCE CONTROL
The AD9949 uses sequence change positions (SCP) and sequence pointers (SPTR) to organize the individual horizontal sequences. Up to four SCPs are available to divide the readout into four separate regions, as shown in Figure 25. The SCP0 is always hard-coded to Line 0, and SCP1 to SCP3 are register programmable. During each region bounded by the SCP, the SPTR registers designate which sequence is used by each signal.
EXTERNAL HBLK SIGNAL
The AD9949 can also be used with an external HBLK signal. Setting the HBLKDIR register (Address 0x40) to high disables the internal HBLK signal generation. The polarity of the external signal is specified using the HBLKPOL register, and the masking polarity of H1 is specified using the HBLKMASK register. Table 21 summarizes the register values when using an external HBLK signal.
SEQUENCE CHANGE OF POSITION 0 (V-COUNTER = 0)
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0 SEQUENCE CHANGE OF POSITION 1 CLAMP AND PBLK SEQUENCE REGION 1 SEQUENCE CHANGE OF POSITION 2
CLAMP AND PBLK SEQUENCE REGION 2
SEQUENCE CHANGE OF POSITION 3 UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
03751-026
CLAMP AND PBLK SEQUENCE REGION 3
Figure 25. Clamp and Blanking Sequence Flexibility
Table 21. External HBLK Register Parameters
Register HBLKDIR HBLKPOL Length 1b 1b Range High/Low High/Low Description Specifies HBLK Internally Generated or Externally Supplied. 1 = External. External HBLK Active Polarity. 0 = Active Low. 1 = Active High. External HBLK Masking Polarity. 0 = Mask H1 Low. 1 = Mask H1 High.
HBLKEXTMASK
1b
High/Low
Rev. B | Page 23 of 36
AD9949
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter (see Figure 26). As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge occurs.
VD
HD
H-COUNTER RESET
CLI
H-COUNTER X (PIXEL COUNTER) PxGA GAIN X REGISTER
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
1
2
3
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2
3
2
3
NOTES 1. INTERNAL H-COUNTER IS RESET 7 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0). 2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE. 3. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
Figure 26. H-Counter Synchronization
Rev. B | Page 24 of 36
03751-027
AD9949 POWER-UP PROCEDURE
RECOMMENDED POWER-UP SEQUENCE
When the AD9949 is powered up, the following sequence is recommended (refer to Figure 27 for each step): 1. 2. 3. Turn on the power supplies for the AD9949. Apply the master clock input, CLI, VD, and HD. Although the AD9949 contains an on-chip, power-on reset, a software reset of the internal registers is recommended. Write a 1 to the SW_RST register (Address 0x10), which resets the internal registers to their default values. This bit is self-clearing and automatically resets back to 0. The Precision Timing core must be reset by writing a 0 to the TGCORE_RSTB register (Address 0x12) followed by writing a l to the TGCORE_RSTB register. This starts the internal timing core operation. 5. Write a 1 to the PREVENTUPDATE register (Address 0x14). This prevents the updating of the serial register data. Write to the desired registers to configure high speed timing and horizontal timing. Write a 1 to the OUT_CONTROL register (Address 0x11). This allows the outputs to become active after the next VD/HD rising edge. Write a 0 to the PREVENTUPDATE register (Address 0x14). This allows the serial information to be updated at next VD/HD falling edge. The next VD/HD falling edge allows register updates to occur, including OUT_CONTROL, which enables all clock outputs.
6. 7.
8.
4.
9.
VDD (INPUT)
1
CLI (INPUT)
2
tPWR
SERIAL WRITES
3
4
5
6
7
8
VD (OUTPUT) 2 HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG
... ...
9 ODD FIELD 1H
1V
...
EVEN FIELD
...
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS UPDATED AT VD/HD EDGE
Figure 27. Recommended Power-Up Sequence
Rev. B | Page 25 of 36
03751-028
AD9949 ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9949 signal processing chain is shown in Figure 28. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. Table 22. Adjustable CDS Gain
Operation Register Bits D11 D10 0 0 0 1 1 0 1 1 CDS Gain 0 dB -2 dB -4 dB 0 dB Max CDS Input 1.0 V p-p 1.2 V p-p 1.6 V p-p 1.0 V p-p
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V to be compatible with the 3 V supply voltage of the AD9949.
PxGA
The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to multiplex its gain value on a pixel-to-pixel basis (see Figure 29). This allows lower output color pixels to be gained up to match higher output color pixels. Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. The four different gain values are switched according to the color steering circuitry. Three different color steering modes for different types of CCD color filter arrays are programmable in the AFE CTLMODE register at Address 0x03 (see Figure 33 to Figure 35 for timing examples). For example, progressive steering mode accommodates the popular Bayer arrangement of red, green, and blue filters (see Figure 30).
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 17 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and the CCD signal level, respectively. The placement of the SHP and SHD sampling edges is determined by the setting of the SAMPCONTROL register located at Address 0x63. Placement of these two clock signals is critical in achieving the best performance from the CCD. The gain in the CDS is fixed at 0 dB by default. Using Bits D10 and D11 in the AFE operation register, the gain may be reduced to -2 dB or -4 dB. This allows the AD9949 to accept an input signal of greater than 1 V p-p. See Table 14 for register details.
1.0F 1.0F REFB REFT 1.0V DC RESTORE 1.5V SHP SHD 1.0F CCDIN 0dB ~ 18dB PxGA 6dB ~ 42dB VGA 2V FULL SCALE OUTPUT DATA LATCH 12 DOUT INTERNAL VREF 2.0V
AD9949
DOUT PHASE
CDS 0dB, -2dB, -4dB
12-BIT ADC
PxGA GAIN REGISTERS
VGA GAIN REGISTER
DAC
OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER 8
SHP
DOUT SHD PHASE
CLPOB PBLK
CLAMP LEVEL REGISTER
Figure 28. Analog Front End Functional Block Diagram
Rev. B | Page 26 of 36
03751-029
PRECISION TIMING GENERATION
V-H TIMING GENERATION
AD9949
VD HD SHP/SHD COLOR STEERING CONTROL 2 GAIN0 4:1 4:1 MUX MUX 8 GAIN1 GAIN2 GAIN3 PxGA GAIN REGISTERS 3 PxGA STEERING MODE SELECTION CONTROL REGISTER BITS D0 TO D1
A third type of readout uses the Bayer pattern divided into three different readout fields. The 3-field mode should be used with this type of CCD (see Figure 32). The color steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user with vertical (VD) and horizontal (HD) sync pulses. For timing information, see Figure 35.
CCD: 3-FIELD READOUT FIRST FIELD
03751-030
COLOR STEERING MODE: THREE FIELD LINE0 LINE1 LINE2 GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN0, GAIN1, GAIN0, GAIN1, ...
CDS
PxGA
VGA
R Gb
Gr B Gr B
R Gb R Gb
Gr B Gr B
Figure 29. PxGA Block Diagram
R
CCD: PROGRESSIVE BAYER
COLOR STEERING MODE: PROGRESSIVE GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN0, GAIN1, GAIN0, GAIN1, ...
03751-031
Gb
R Gb R Gb
Gr B Gr B
R Gb R Gb
Gr B Gr B
LINE0 LINE1 LINE2
SECOND FIELD Gb R Gb R B Gr B Gr Gb R Gb R B Gr B Gr LINE0 LINE1 LINE2 GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN2, GAIN3, GAIN2, GAIN3, ...
Figure 30. CCD Color Filter Example--Progressive Scan
Gb
B
Gb
B
CCD: INTERLACED BAYER EVEN FIELD R R R R Gr Gr Gr Gr R R R R Gr Gr Gr Gr LINE0 LINE1 LINE2
COLOR STEERING MODE: INTERLACED GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN0, GAIN1, GAIN0, GAIN1, ...
Figure 32. CCD Color Filter Example--Three-Field Readout
ODD FIELD Gb Gb Gb Gb B B B B Gb Gb Gb Gb B B B B LINE0 LINE1 LINE2 GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN2, GAIN3, GAIN2, GAIN3, ...
03751-032
Figure 31. CCD Color Filter Example--Interlaced Readout
Rev. B | Page 27 of 36
03751-033
The same Bayer pattern can also be interlaced, and the interlaced mode should be used with this type of CCD (see Figure 31). The color steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user with vertical (VD) and horizontal (HD) sync pulses. For timing information, see Figure 34.
THIRD FIELD R Gb R Gr B Gr R Gb R Gr B Gr LINE0 LINE1 LINE2 GAIN0, GAIN1, GAIN0, GAIN1, ... GAIN2, GAIN3, GAIN2, GAIN3, ... GAIN0, GAIN1, GAIN0, GAIN1, ...
AD9949
FIELDVAL
FIELDVAL = 0
FIELDVAL = 0
VD
HD
PxGA GAIN X REGISTER
X
0
1
0
1
2
3
2
3
0
1
0
1
0
1
0
1
2
3
2
3
0
1
0
1
0
NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES. 3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES.
Figure 33. PxGA Color Steering--Progressive Mode
FIELDVAL
FIELDVAL = 0
FIELDVAL = 1
FIELDVAL = 0
VD
HD
PxGA GAIN REGISTER X
X
0
1
0
1
0
1
0
1
2
3
2
3
2
3
2
3
0
1
0
1
0
1
0
1
NOTES 1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE. 2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE. 3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER 0 (FIELDVAL = 0) OR 2 (FIELDVAL = 1). 4. FIELDVAL WILL TOGGLE BETWEEN 0 AND 1 ON EACH VD FALLING EDGE.
Figure 34. PxGA Color Steering--Interlaced Mode
FIELDVAL
FIELDVAL = 0
FIELDVAL = 1
FIELDVAL = 2
VD
HD
PxGA GAIN X REGISTER
X
0
1
0
1
2
3
2
3
2
3
2
3
1
0
1
0
0
1
0
1
2
3
2
3
NOTES 1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE. 2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE. 3. FIELDVAL = 2 (START OF THIRD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE. 4. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES. 5. FIELDVAL WILL INCREMENT AT EACH VD FALLING EDGE, REPEATING THE 0...1...2...0...1...2 PATTERN.
Figure 35. PxGA Color Steering--Three-Field Mode
Rev. B | Page 28 of 36
03751-036
03751-035
03751-034
AD9949
The PxGA gain for each of the four channels is variable from 0 dB to 18 dB in 512 steps, specified using the PxGA GAIN01 and PxGA GAIN23 registers. The PxGA gain curve is shown in Figure 36. The PxGA GAIN01 register contains nine bits each for PxGA Gain0 and Gain1, and the PxGA GAIN23 register contains nine bits each for PxGA Gain2 and Gain3.
18
42
36
30
VGA GAIN (dB)
24
18
15
12
PxGA GAIN (dB)
12
03751-038
0
9
0
127
255 383 511 639 767 VGA GAIN REGISTER CODE
895
1023
6
Figure 37. VGA Gain Curve (PxGA Not Included)
3
OPTICAL BLACK CLAMP
0 64 128 192 256 320 384 448 511
PxGA GAIN REGISTER CODE
Figure 36. PxGA Gain Curve
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB. The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain can be calculated for any gain register value by using the equation Gain (db) = (0.0351 x Code) + 6 dB where the code range is 0 to 1023. There is a restriction on the maximum amount of gain that can be applied to the signal. The PxGA can add as much as 18 dB, and the VGA is capable of providing up to 42 dB. However, the maximum total gain from the PxGA and VGA is restricted to 42 dB. If the registers are programmed to specify a total gain higher than 42 dB, the total gain is clipped at 42 dB.
03751-037
0
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the clamp level register. The value can be programmed between 0 LSB and 255 LSB in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a DAC. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the postprocessing, the AD9949 optical black clamping may be disabled using Bit D2 in the OPRMODE register. When the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulse widths may be used, but clamp noise may increase and the ability to track low frequency variations in the black level will be reduced. See the Horizontal Clamping and Blanking and Applications Information sections for timing examples.
DIGITAL DATA OUTPUTS
The AD9949 digital output data is latched using the DOUT phase register value, as shown in Figure 28. Output data timing is shown in Figure 19 and Figure 20. It is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the ADC. Programming the AFE control register Bit D4 to a 1 sets the output latches transparent. The data outputs can also be disabled (three-stated) by setting the AFE control register Bit D3 to a 1. The data output coding is normally straight binary, but the coding may be changed to gray coding by setting the AFE control register Bit D5 to a 1.
ADC
The AD9949 uses a high performance ADC architecture, optimized for high speed and low power. DNL performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. See Figure 9 and Figure 10 for typical linearity and noise performance plots for the AD9949.
Rev. B | Page 29 of 36
AD9949 APPLICATIONS INFORMATION
CIRCUIT CONFIGURATION
The AD9949 recommended circuit configuration is shown in Figure 38. Achieving good image quality from the AD9949 requires careful attention to PCB layout. All signals should be routed to maintain low noise performance. The CCD output signal should be directly routed to Pin 27 through a 0.1 F capacitor. The master clock CLI should be carefully routed to Pin 25 to minimize interference with the CCDIN, REFT, and REFB signals. The digital outputs and clock inputs are located on Pins 1 to 13 and Pins 31 to 40 and should be connected to the digital ASIC away from the analog and CCD clock signals. Placing series resistors close to the digital output pins may help to reduce digital code transition noise. If the digital outputs must drive a load larger than 20 pF, buffering is recommended to minimize additional noise. If the digital ASIC can accept gray code, the AD9949's outputs can be selected to output data in gray code format using the control register Bit D5. Gray coding helps reduce potential digital transition noise compared with binary coding. The H1-H4 and RG traces should have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1-H4 from the capacitive load of the CCD. If possible, physically locating the AD9949 closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9949 to the CCD.
3V ANALOG SUPPLY VD/HD/HBLK INPUTS CLP/BLK OUTPUT 4 0.1F SERIAL INTERFACE
GROUNDING AND DECOUPLING RECOMMENDATIONS
As shown in Figure 38, a single ground plane is recommended for the AD9949. This ground plane should be as continuous as possible, particularly around Pins 23 to 30. This ensures that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All high frequency decoupling capacitors should be located as close as possible to the package pins. It is recommended that the exposed paddle on the bottom of the package be soldered to a large pad, with multiple vias connecting the pad to the ground plane. All the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. There should also be a 4.7 F or larger bypass capacitor for each main supply--AVDD, RGVDD, HVDD, and DRVDD--although this is not necessary for each individual pin. In most applications, it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may be used for DRVDD, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The reference bypass pins (REFT, REFB) should be decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin.
CLP/PBLK
D0 (LSB)
3
HBLK
DVDD
DVSS
HD VD 33 SCK 32 SDI
35 34
40
39
38
37
36
31
SL
D1 1 D2 2 D3 3 D4 4 3V DRIVER SUPPLY DRVSS 5 + DRVDD 6 D5 7 D6 8 D7 9 D8 10
PIN 1 IDENTIFIER
30 29 28
REFB REFT
1F 1F 0.1F 0.1F + CCD SIGNAL MASTER CLOCK INPUT 3V ANALOG SUPPLY
AVSS 27 CCDIN
AD9949
TOP VIEW
26 25 24 23
AVDD CLI TCVDD
4.7F 0.1F
TCVSS 22 RGVDD
21
0.1F
4.7F
RG
RG OUTPUT RG DRIVER SUPPLY 4.7F
D9 11
HVDD 17
D10 12 (MSB) D11 13
HVSS 16
H3 18
H2 15
RGVSS 20
H1 14
H4 19
DATA OUTPUTS
12
0.1F
+
4 H1 TO H4
Figure 38. Recommended Circuit Configuration
Rev. B | Page 30 of 36
03751-039
0.1F
+
H DRIVER SUPPLY 4.7F
AD9949
DRIVING THE CLI INPUT
The AD9949's master clock input (CLI) may be used in two different configurations, depending on the application. Figure 41 shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is used, the master clock signal should be at standard 3 V CMOS logic levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor may be used between the clock source and the CLI input. In this configuration, the CLI input is self-biased to the proper dc voltage level of approximately 1.4 V. When the ac-coupled technique is used, the master clock signal can be as low as 500 mV in amplitude.
AD9949
25
CLI ASIC
MASTER CLOCK
Figure 41. CLI Connection, DC-Coupled
AD9949
18 19 14 15 21
27
CCDIN
AD9949
25
CLI 1nF
H3
H4
H1
H2
RG
LPF
ASIC
SIGNAL OUT
Figure 42. CLI Connection, AC-Coupled
H1 H2 RG
03751-040
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 43 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back. To configure the AD9949 horizontal signals for this CCD, three sequences can be used. Figure 44 shows the first sequence that should be used during vertical blanking. During this time, there are no valid OB pixels from the sensor, so the CLPOB signal is not used. PBLK may be enabled during this time, because no valid data is available. Figure 45 shows the recommended sequence for the vertical OB interval. The clamp signals are used across the whole lines in order to stabilize the clamp loop of the AD9949. Figure 46 shows the recommended sequence for the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signal.
CCD IMAGER
Figure 39. CCD Connections (2 H-Clock)
AD9949
14 15 18 19 21
27
CCDIN
H1
H2
H3
H4
RG
SIGNAL OUT
H3
H4
RG H2 H1
CCD IMAGER
Figure 40. CCD Connections (4 H-Clock)
Rev. B | Page 31 of 36
03751-041
03751-043
MASTER CLOCK
03751-042
AD9949
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
V
EFFECTIVE IMAGE AREA
USE SEQUENCE 3
10 VERTICAL OB LINES
USE SEQUENCE 2 H 4 OB PIXELS HORIZONTAL CCD REGISTER
03751-044
48 OB PIXELS
28 DUMMY PIXELS
Figure 43. Example CCD Configuration
SEQUENCE 1: VERTICAL BLANKING CCDIN INVALID PIX VERTICAL SHIFT DUMMY INVALID PIXELS VERT SHIFT
SHP SHD H1/H3 H2/H4
HBLK PBLK CLPOB
03751-045
Figure 44. Horizontal Sequence During Vertical Blanking
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES OPTICAL BLACK CCDIN VERTICAL SHIFT DUMMY OPTICAL BLACK VERT SHIFT
SHP SHD H1/H3 H2/H4
HBLK PBLK
03751-046
CLPOB
Figure 45. Horizontal Sequences During Vertical Optical Black Pixels
Rev. B | Page 32 of 36
AD9949
SEQUENCE 3: EFFECTIVE PIXEL LINES OPTICAL BLACK CCDIN VERTICAL SHIFT DUMMY OB EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT
SHP SHD H1/H3 H2/H4
HBLK PBLK
03751-047
CLPOB
Figure 46. Horizontal Sequences During Effective Pixels
Rev. B | Page 33 of 36
AD9949 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOTTO M VIEW)
4.25 4.10 SQ 3.95
10 11
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm x 6 mm Body (CP-40) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9949KCP AD9949KCPRL AD9949KCPZ1 AD9949KCPZRL1 AD9949AKCPZ1, 2 AD9949AKCPZRL1, 2 Temperature Range -20C to +85C -20C to +85C -20C to +85C -20C to +85C -20C to +85C -20C to +85C Package Description 40-Lead Lead Frame Chip Scale Package (LFCSP) 40-Lead Lead Frame Chip Scale Package (LFCSP) 40-Lead Lead Frame Chip Scale Package (LFCSP) 40-Lead Lead Frame Chip Scale Package (LFCSP) 40-Lead Lead Frame Chip Scale Package (LFCSP) 40-Lead Lead Frame Chip Scale Package (LFCSP) Package Option CP-40 CP-40 CP-40 CP-40 CP-40 CP-40
1 2
Z = PB-free part. The AD9949A is recommended for new designs and supports CCD line lengths > 4096 pixels.
Rev. B | Page 34 of 36
AD9949 NOTES
Rev. B | Page 35 of 36
AD9949 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03751-0-11/04(B)
Rev. B | Page 36 of 36

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